In order to allow integrated circuits (ICs) from various manufacturers to communicate with each other, various standards have been developed specifying required input/output (I/O) behavior at IC pins. Such I/O standards may provide guidelines or requirements for various signal characteristics such as voltage, current, power and timing. Most systems adhere to at least one such standard, and typically require that devices in the system adhere to the standards being used. Therefore, the ability to meet such I/O standards is a strong commercial advantage.
In particular, designing an IC to meet voltage requirements of an I/O standard can be especially challenging. As IC fabrication processes improve and the minimum feature size on an IC decreases, the voltage level required to operate such ICs also decreases. Current IC processes can typically operate at approximately 1.3V and even lower voltages will be possible soon as technology continues to improve. However, ICs fabricated using these processes often need to be compatible with I/O standards that have not changed and that may require significantly higher voltages. A chip will often be divided into two sections: a core section, which contains the main logical, storage and processing circuitry of the IC, and an I/O section, which contains the circuitry that allows the IC to interface with the system. This division permits different power sources to be used with the different sections. For example, the core can be powered by one voltage source for internal use, VDDI, that is dictated, in part, by the process, while the I/O section can be powered by a different voltage source for external interface, VDDE, that is dictated by the I/O standard. Depending on the particular I/O standard and other IC and system architectural considerations, VDDE can be equal to VDDI, or VDDE can be a voltage level greater than VDDI. For an example, VDDI can be 1.8V while VDDE is 2.5V or 3.3V.
FIG. 1 shows a prior art output driver circuit 100. This circuit, which would be part of the I/O section of an IC, is used to drive an output signal from the IC to another component in the system. The circuit has an input signal IN (node 104), an output enable signal OUT—EN (node 108), and produces an output signal at output PAD (node 170). Note that circuit 100 shows an output driver only, but input receiver circuitry could be added without significantly affecting the output functionality of the output driver. Circuit 100 contains tri-state buffers 121, selectively enabled by a control signal, and inverters 123. Each of the buffers and inverters is connected to an appropriate power supply, either VDDI or VDDE, as shown. Output pullup device 147 of the output driver circuit, a PMOS transistor, operates to pull PAD 170 to a logic high value. Output pulldown device 157, an NMOS transistor, pulls PAD 170 to a logic low. If the OUT—EN signal is not asserted, then the output driver is disabled and output driver circuit 100 is in a high impedance state. If the OUT—EN signal is asserted, then the output at PAD 170 will follow the input at IN. For example, if IN is a logic high, then PAD 170 will also be a logic high, and vice versa.
In the example shown in FIG. 1, the core operates at voltage VDDI, which is lower than voltage VDDE. VDDE can be 2.5V, 3.3V, or any other voltage that is required for the applicable I/O standard. This division of power supplies allows the core to operate more efficiently at a lower voltage, but provides a higher voltage source for driving the output. Note that in this example, GNDI and GNDE are the same voltage level of zero volts. One reason GNDI and GNDE are separated in some ICS is to isolate the core from the I/O and reduce the effects of noise from one section on the other. However, the differences between GNDI and GNDE are not important for the purposes of this discussion and in the examples herein, GNDI and GNDE are both at a voltage level of 0V. Output pullup 147 is connected to VDDE so that when pullup 147 is on, the output at PAD 170 will be driven to VDDE. In order to fully turn off pullup 147 (when the output at PAD 170 should be a logic low), a level shifter 140 is used to drive the gate of pullup 147. Level shifter 140 shifts voltage levels, so, for example, an input having a voltage range from 0V to 1.8V (VDDI) can be shifted to having a range from 0V to 2.5V/3.3V (VDDE). An example of a standard level shifter is shown in FIG. 3. Other level shifting circuits will be known to those of ordinary skill in the art. By shifting the voltage range applied to the gate of PMOS pullup device 147 from VDDI to VDDE, pullup 147 can be fully turned off for better performance. Note that the level shifters used in the examples described herein are inverting level shifters (for example, a logic low input results in a logic high output at the shifted voltage levels, and vice versa); however, a non-inverting level shifter can be substituted (with appropriate circuit modifications) in accordance with an embodiment of the present invention.
In circuit 100, no level shifter is necessary for fully turning off pulldown 157 because GNDI and GNDE are both 0V, and, therefore, pulldown 157 is already fully turned off when the output at PAD 170 should be a logic high. However, since the gate of pulldown 157 is driven only to VDDI (and not to VDDE, which is greater than VDDI) when it is on, pulldown 157 will be slower than pullup 147. This asymmetry causes skew between the rise time and fall time of the signal at PAD 170 when VDDE is greater than VDDI. One solution is to increase the size (width) of pulldown 157 to pull down node 170 more quickly, or to add an additional pulldown device 167 in parallel (which effectively increases the size of pulldown 157).
Since ICs are typically designed for a particular application and for use in a particular system (or type of system), they are usually optimized for the I/O standards of that application and system. Optimization can take into account such factors as speed, timing, power, current, etc. If an IC designed for one standard is used within a system for any other I/O standard, it will perform sub-optimally, and may not work at all. For example, in FIG. 1, additional pulldown 167 speeds up the pulldown path and balances the skew for the case when VDDE is greater than VDDI. If, however, the same IC is used in a system employing a different I/O standard where VDDE equals VDDI, additional pulldown 167 causes the skew to become unbalanced, since the pulldown path is now much faster than the pullup path. In order to use an existing IC in a different system with different I/O standards, it can be necessary to redesign the IC, potentially at great expense.
A programmable logic device (PLD) is a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. In particular, a PLD could be programmed differently depending on the I/O standard in use. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, multipliers, processors, and so forth).
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to programmable I/O resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices.
For all of these programmable logic devices, the functionality of the device is controlled by data bits provided to the device for that purpose, and altering the data bits provided can change the configuration of a PLD. In the example shown in FIG. 1, data bit OUT—GROUP—EN at node 106 is used to selectively enable additional pulldown 167. The data bit can be configured to enable additional pulldown 167 when VDDE is greater than VDDI, and disable it when VDDE equals VDDI. The data bits must be stored in some kind of memory, which can be volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), non-volatile memory (e.g., FLASH memory, as in some CPLDs), or any other type of memory cell. In any case, in order to program a particular CLB, IOB, function block, or other programmable resource in the PLD, some form of memory must be set aside to control the functionality of the programmable resource. This memory consumes limited resources on the IC by occupying part of the area of the IC and requiring access to an interface for loading the memory with the appropriate configuration data bits.
In addition, such memory can typically only be updated during a configuration phase of the PLD. Once the PLD has been configured and is in full operation, it is difficult to reconfigure the PLD without suspending operation. Normally, the voltage level of VDDE will be established at power-up and will remain constant while the circuit is in use. A change in the I/O voltage supply, which can be necessitated, for example, by a change in the relevant I/O standard or a change in the system architecture, is a relatively rare event that would most likely require a user to power down the system, providing an opportunity to reconfigure the PLD, in order to make the change. A user's particular application, however, may require switching the VDDE power supply “on the fly,” that is, while the IC is powered on and in operation. Furthermore, reconfiguring the PLD may involve reprogramming other devices in the system and may require additional design time.
Therefore, a need exists for a way to automatically reconfigure an IC to comply with different I/O standards with a minimal cost in resources. A need also exists for a way to reconfigure a circuit automatically when the voltage of a power supply is changed.